Supports up to 4 data lanes plus 1 clock lane per link. A complete 4-lane configuration reaches an aggregate throughput of 18 Gbps . Voltage Signaling:
Additionally, a new during the initialization handshake allows the receiver to calibrate lane-to-lane skew down to 0.1 UI (Unit Interval)—approximately 22 picoseconds at 4.5 Gbps. This is a major improvement over v1.2’s less formal skew tolerance. mipi d phy 20 specification top